Browse Prior Art Database

Error Detection and Fault Isolation Packaging for Circuit Chips

IP.com Disclosure Number: IPCOM000056765D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Overfield, RB Patel, MP Singh, P [+details]

Abstract

A method is described which allows packaging of two chips on a single substrate for fault isolation in a Master-Slave configuration thereby reducing the cost of an extra package and area on a printed circuit board (PCB). As one attempts to package more than one chip on a substrate, the need to increase the area and I/O pins becomes apparent. High I/O requirements are solvable by using multilayer ceramic (MLC) substrates, but at an increased cost. Under special circumstances when I/O's from two chips can be shorted together, then two chips can be assembled on a simpler master chip (MC) substrate. The procedure of packaging such an arrangement is shown in Fig. 1 and described below. (Image Omitted) The fault-isolation technique with fault-tolerant master/slave checking is used for error detection on VLSI chips.