Code for Leveling BUS Driver Current
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14
The trend in digital logic design is to larger chips on larger carriers. The average circuit power on the chips is decreasing but the power of the driver circuits for chip-to-chip communication cannot be reduced correspondingly. It is becoming increasingly difficult to provide enough drive capability on the chip to serve the very high circuit counts that can be realized. A means of encoding data being transmitted from chip to chip so the power demands of the driving circuits are reduced is described. Specifically, it is a means of encoding the data being transmitted on parallel digital busses to reduce both the total current and the change in the total current (delta I) being transmitted over the bus.