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Pre-Decoder With Address Increment Circuits

IP.com Disclosure Number: IPCOM000056809D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Sunaga, T [+details]

Abstract

This is a pre-decoder circuit with a static shift register function. It realizes a high speed access of continuous memory addresses. The first memory address is latched by a conventional method, but the subsequent addresses are accessed by shifting the pre-decoded data. Because it is applicable to not only column but also row pre-decoders, there is no limit in an address range to be accessed continuously. (Image Omitted) Fig. 1 shows a circuit schematic for the lowest 4 address bits. The left half is the conventional pre-decoder circuit which consists of inverters and NAND gates. The right half is the static shift register. Its parallel outputs, DEC01-DEC14, are connected to a main decoder. /1, /2, /3, and /4 are clock pulses which control the shift and latch operation.