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Circuit Using CMOS That Has Redundant Duality

IP.com Disclosure Number: IPCOM000056909D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Banker, DC Dorler, JA Maley, GA [+details]

Abstract

This article concerns the employment of redundancy in complementary metal oxide semiconductor (CMOS) circuits to achieve a logic network that is tolerant of open or shorted interconnecting wires. A CMOS circuit designed to be tolerant to open or shorted interconnecting wires is essential to improved chip yields. The CMOS circuit illustrated in Fig. 1 contains the four characteristics essential to such improvement. These are: 1) Two independent outputs, e.g., O1 and O2. 2) Signal line shorts must produce a logic "OR" or a logic "AND" connective. (Image Omitted) 3) An open signal line must produce the non-controlling input state necessary to control. 4) The input logic connective must be the dual of the logic connective formed by the undesired short. Fig.