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TESTER-LOOP-INDEPENDENT SIMULATION in the PRESENCE of MEMORY

IP.com Disclosure Number: IPCOM000056910D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
McAnney, WH Savir, J [+details]

Abstract

Pseudo-random testing is used on a structure containing embedded memory. A test failure requires diagnosis to the fault location. It is assumed that probing cannot be used. One diagnostic approach is fault simulation, a tedious process because of the error latency caused by the memory. A second approach is to add circuitry to bypass the memory inputs around to primary outputs of the structure. A new method is described here that uses tester-loop-independent fault simulation as a solution to this diagnostic problem. (Image Omitted) An LSSD logic structure that contains a random-access memory as shown in Fig. 1 is tested with pseudo random patterns. The responses of the structure are compressed in a single- or multiple-input signature register. A faulty signature is observed after test completion.