Browse Prior Art Database

Transistor Gated CTS Memory Cell

IP.com Disclosure Number: IPCOM000056932D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A transistor gated complementary transistor switch (CTS) memory cell is described in this article which offers a fast write operation with high immunity against soft errors, a high packaging density, and flexible organization. The electrical circuit of the disclosed CTS cell includes six transistors, T1, T2, T3, T4, T5 and T6, as shown in Fig. 1. The transistor gated CTS cell layout is sketched in Fig. 2. T5 and T6 are driven by gate line GL, operating in both normal and inverse mode. Operations are as follows: Standby: I/O transistors T5 and T6 are both off: Data polarity is maintained with the complementary inverters T1, T4 and T2, T3.