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Scratch-Pad Floating-Point Registers for High-Performance Computers

IP.com Disclosure Number: IPCOM000056939D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Rodriguez, JR [+details]

Abstract

A technique is described whereby scratch-pad floating-point registers are employed, in internally functioning binary floating-point computer architecture, so as to eliminate critical path delays in the processing of data. The concept is consistent with IEEE Standard 754, relative to binary floating-point architecture, such that operands performed in the internal format are stored in scratch-pad registers and routed directly to arithmetic logic units without having to be routed through pack/ unpack logic. Floating-point (FP) architecture, which uses data formats and conversion instructions consistent with IEEE Standard 754 on binary floating-point arithmetic, defines data operands in two integer formats and three floating-point formats.