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Pipelining of Floating Point Multiply Unit With Common Input/Output Disclosure Number: IPCOM000056951D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Keung, T Suarez, GA [+details]


A technique is described for pipelining multiplication operations in a floating point processor whose multiply unit is implemented with common input/output (I/O). The technique minimizes the execution time while maintaining optimum overlapped throughput in the multiply unit. (Image Omitted) The concept centers around a dual-function floating point processor which has a centralized control structure to support both hexadecimal (hex) and IEEE binary (bin) operations. Five different operand formats are supported: binary single, double, double extended and hex, long and short. Typically, the use of common I/O limits the overlap capability when attempting to overlap the loading of new operands with the transfer of the previous result.