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Vias for Chip Wiring

IP.com Disclosure Number: IPCOM000056975D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Anderson, H Dahmen, M Klein, K Pollman, K Wagner, O Zuehlke, R [+details]

Abstract

Very large-scale integrated (VLSI) chips are wired by metallizations. These metallizations, arranged on top of each other, are separated by an insulating layer. Wiring channels, forming a wiring pattern, are defined on the first and the second metallization. At particular crossings of the wiring channels, holes (vias) are provided in the insulating layer. In these vias, the metal of a conductor M2 of the second top metallization contacts a conductor M1 of the first metallization. Schematic sectional plan views of the first and the second metallization are shown in the figures. Fig. 1 shows general design rules A and B for vias. Observance of these rules prevents shorts in the via regions between conductors M1 and M2. Design rules C and D prevent shorts in M1 and M2, respectively. Fig. 2 shows a standard via.