Length Minimization Algorithm for a Wire With Jogs
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14
A method is provided for minimizing orthogonal wire length in integrated circuits after a loose layout of the integrated circuit has been compacted. The method permits jogs to be introduced into the horizontal wire to which the orthogonal wires are connected such that the horizontal wire can have segments at different constant y (vertical) locations. Thus, the method is in contrast to other wire minimization techniques.