Adaptive Compilation for Delayed Branches of Pipelined Computer Processing
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14
A technique is described whereby branch statistics and conditional execution, after a delayed branch, improves the performance of pipelined computer processors. The technique produces results comparable to branch-history methods, while using a smaller memory. The objective of the concept is to reduce the average number of cycles after the decoding of a conditional branch instruction in pipelined computer architecture. The outcome of a branch condition may not be available until several cycles after a conditional branch instruction is decoded. Since the outcome is unknown, the processor pipeline cannot continue filling the memory with instructions for execution. This results in performance degradation because future cycles may have no executable instructions available. This causes a branch- resolution delay.