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LOW TEMPERATURE FABRICATION PROCESS FOR HIGH-PERFORMANCE MOSFETs

IP.com Disclosure Number: IPCOM000057006D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Meyerson, BS Nguyen, TN Sai-Halasz, GA [+details]

Abstract

A technique is described whereby high performance MOSFETs are fabricated by means of a low thermal process which combines low-temperature in situ-doped epitaxy, plasma assisted oxidation and novel dopant species for source/drain formation. The concept is an improvement over fabrication processes which used conventional channel implant doping techniques so as to obtain NMOS and PMOS devices with superior functional characteristics. In the fabrication of conventional field-effect transistors (FETs), typically as dimensions shrink, the concentration of the dopant increases so as to achieve the proper threshold voltage.