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L1/L2 Organization Multiple Level Cache for Computer System Data Sharing

IP.com Disclosure Number: IPCOM000057015D
Original Publication Date: 1988-Feb-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Liu, L [+details]

Abstract

A technique is described whereby an L1/L2 multiple level cache memory is used for sharing data at main memory between multiple computer systems. Multiprocessor performance is enhanced by relieving the dependency on the L3 cache. Within each memory cluster, the L1/L2 multiple level cache memories are organized in the usual accepted mode, e.g., store-thru L1's and store-in L2. However, for shared data lines belonging to the shared memory portion, a store-thru is provided from L1 to both L2 and L3 multiple level caches. Since it is essential for high performance computer processors to use multiple level cache hierarchies to attain proper performance, the concept focuses on the environment in which a Central Electric Complex (CEC) is partitioned into multiple clusters.