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Fast Cache Access Based on Most Recently Used Hits

IP.com Disclosure Number: IPCOM000057017D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Chang, JH Chao, HH Tang, JY So, K [+details]

Abstract

A technique is described whereby accessing cache memories in high speed computers takes advantage of the high percentage of most recently used (MRU) region hits. A fast logic path is provided to select double words within the MRU line of a set from the cache and deliver the double words to the central processing unit (CPU) in a single cycle. The regular path is retained for back-up purposes if the access is not to the MRU region. A simplified data path diagram for a conventional cache accessing scheme is shown in Fig. 1. To address a byte in a 128 KB real cache requires 17 real bits. The page offset for a 4K page has 12 real bits. In order to do address translation and cache directory look-up concurrently, a 32-way associative cache is required.