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Improved Tungsten Gate Process for Submicron CMOS Devices

IP.com Disclosure Number: IPCOM000057019D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Davari, B Ray, AK [+details]

Abstract

A technique is described whereby an improved fabrication process of submicron CMOS semiconductor devices, using tungsten as a mid-gap material, eliminates tungsten oxidation problems while providing compatibility with conventional silicon technology. Tungsten, used as a mid-gap material, for gates in half micron CMOS devices typically provides low resistivity and proper workfunction while improving field-effect transistor (FET) device characteristics. It also provides compatibility with current interconnection technology. However, processing problems occur, during the fabrication process, with integrating the tungsten metallurgy with conventional silicon technology. One problem area is the oxidation of silicon, preferentially, in the source-drain (S/D) regions, after tungsten gates are defined, as shown in Fig. 1.