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Self-Reference (Hybrid) Cascode Circuit

IP.com Disclosure Number: IPCOM000057031D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Leung, WC [+details]

Abstract

A circuit configuration has been proposed for providing a low voltage cascode current switch emitter follower for high performance semiconductor applications where power dissipation is a concern. It consists of a clamping scheme and a self-reference scheme. The existing hybrid cascode is shown in Fig. 1. It consists of cross-coupled Schottky diodes at the collector nodes which provide a clamped output swing and a differential input pair for the lower signal level. In the circuit INA1, INA2...INB1, INB2....are the normal simple ended inputs while INA and INB are the differential inputs. Its noise margin is relatively poor since its outputs are not compensated and are a function of the up level of the differential inputs INA and INB. (Image Omitted) Through use of the clamping scheme shown in Fig.