Appended "H" Matrix
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14
A method is disclosed whereby error correcting codes (ECCs) can be extended beyond data error detection and correction to include the detection of addressing errors. This approach encodes address selection information into the check bit fields associated with "H" matrices. When the data is being checked for errors, an address comparison (Image Omitted) is also done by the ECC facility to verify that data comes from the correct location. The family of single error correction/double error detection (SEC/DED) ECC codes that have been developed for memory products have the property that an odd number of syndrome bits distinguish odd or single errors, while an even number indicate uncorrectable errors. As a result, codes used in eight check bit applications have combinations of 3 and 5 check bits to identify correctable locations.