Memory Access With Error Recovery
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14
A pipeline consisting of five registers is used to overlap memory accesses within a card or between cards. Memory accesses are initiated from the first two while finishing in the third. The fourth and fifth registers allow the address for the failing memory access to be around for two cycles after the fetch completes. The address of the failing fetch is retained for use during error recovery. The address is also available for each fetch during each stage of its execution. This allows stopping during execution, the error recovery, and continuing where accesses left off. Data is output for subsequent fetches immediately, if available, and fetches or refetching data for subsequent fetches as necessary. The pipeline is instrumental in improving performance when ECC Bypass is enabled.