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Method for Implementing Long-To-Extended Precision Floating Point Multiply Operations on a 64-Bit Data Flow Floating Point Processor Disclosure Number: IPCOM000057098D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Garcia, J Mitchell, JA [+details]


When the capability for executing IBM System/370 (S/370) hexadecimal floating point long-precision multiply instructions exists in a hardware unit, a method for providing hardware "hooks" to allow the simulation of the long-to-extended precision multiply instruction can easily be implemented. A relatively inexpensive set of hardware (Image Omitted) improvements described below was included in a single-chip floating point processor. These minor hardware changes allow extended precision 112-bit multiply operations to be efficiently performed on processors designed to operate on 56-bit operands. The Floating Point Assist Processor (FPAP) is a single chip processor unit which performs a total of 26 floating point operations. All computations are implemented as register-to-register instructions.