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Chip I/O Macros Growable and Placeable Within Cell Array Disclosure Number: IPCOM000057106D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

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Erdelyi, CK Nguyen, PH [+details]


A method for placing off chip drivers, receivers and common I/O circuits is reported for use in Standard Cell or Custom VLSI chip designs when these designs utilize three or more metal interconnect levels. The conventional method of placing I/O circuits on VLSI chips is to place them around the periphery of the chip into pre-assigned areas of fixed size. These areas are called sockets. The metal pads used to connect the chip to the module substrate are also placed in the sockets and typically surround the chip in one, two or three rows. One of the problems that the conventional approach produces is a limitation of the number of I/O connections and very crowded wiring around the chip periphery.