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Power Reduction Method for Static CMOS Programmable Logic Arrays (Plas) Disclosure Number: IPCOM000057113D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

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Luckett, GC [+details]


This article describes a static CMOS PLA in which a p-channel FET load device with its gate connected to ground was replaced with a series of three p-channel devices with their gates connected to signal inputs to obtain a seven times power reduction. Previous static CMOS PLA designs (Fig. 1) have used a p-channel FET with the gate connected to ground as a load device for the product term. If any of the inputs A to N is at a high voltage, the product term will be near zero volts and the load device will dissipate power. In Figs. 1 and 2, VDD is the power supply, QPn are p-channel FET load devices, and QNn are n-channel FET pull-down devices. In Fig. 2, the load device has been replaced by three p-channel devices with their gates connected to inputs A, B and C.