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Process Monitoring Feature for LSSD Designs

IP.com Disclosure Number: IPCOM000057131D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Debord, P Galcera, J Glaise, R [+details]

Abstract

This article describes a simple means to monitor the speed and characteristics of logic modules containing a scan string, such as LSSD (low sensitive scan design) register string during reliability tests as well as in the field. The real speed characteristics of the modules can be determined by adding to the scan chain a feedback loop internal to the chip and measuring the frequency of oscillation then entailed. The feedback is added by connecting the output "SCAN OUT" of a given module (1) to a inverter (3) transmitting the signal with the appropriate polarity to input "SCAN IN" of this module. This module (1) containing a LSSD string made up of a plurality of L1-L2 latches begins to oscillate and allows the measure of the frequency of oscillation and dynamic characteristics of the module.