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System/370 Emulator Assist Processor for a Reduced Instruction Set Computer Disclosure Number: IPCOM000057143D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Garcia, J Hannon, ES Kalla, R Mitchell, JA Zareski, DM [+details]


A host processor implementing a Reduced Instruction Set Computer (RISC) architecture may include a separate processor (called an emulator assist processor or EAP) to facilitate efficient emulation of the System/370 (S/370) architecture. This unit controls S/370 instruction fetch and "host system" instruction generation. It also maintains the S/370 Program Status Word information. This processor is microprogram-controlled. In the most fundamental sense, the EAP can be described as an instruction "translator". This processor is provided with memory access authority to allow it to fetch S/370 instructions from a portion of the host system's main memory reserved for S/370 programs.