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Bitline Sense Amp or Bitline Data Drive for Bipolar RAM

IP.com Disclosure Number: IPCOM000057145D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Anderson, FE Walach, AZ [+details]

Abstract

In a bipolar random-access memory (RAM) cell with a conventional resistive sense amplifier (Fig. 1), the decode current would be converted to a differential voltage by R1 and R2. The signal would then appear at emitters of T1 and T2. The disadvantage of this method is that the high impedance of the sense amp, coupled with the bitline capacitance, results in a large time constant. In a newly-designed sense amplifier (Fig. 2), the bitline current shows up at the emitters of T3 and T4. This is converted to a differential voltage by R1 and R2, which then appears at emitters of T1 and T2. This sense amplifier behaves like a common base sense amplifier to provide very low impedance to the bitlines. This circuit configuration will minimize the delays due to the effective bitline capacitance.