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One-Transistor Bistable Circuit

IP.com Disclosure Number: IPCOM000057155D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Van Zeghbroeck, BJ Wolf, P [+details]

Abstract

A latch, Schmitt trigger and memory cell circuit is proposed requiring only one transistor, e.g., a MESFET, and making use of a negative input resistance that is observed at comparitively high drain voltages. The circuit can be realized in III/V, as well as in silicon technology. (Image Omitted) Fig. 1 shows the IG vs VG input characteristic of a 0.5 um GaAs MESFET with a drain voltage VD of 6.5 V. The negative current is due to holes which are generated by impact inonization in the region between gate and drain, and which recombine at the Schottky gate. At larger voltages VG, when the diode is forward biased, the current becomes positive again. A load line LOAD is also shown. The intersections of the load line with the IG/VG curve form the possible operating points, two of which (A and B) are stable. Fig.