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Content Addressable Memory Cell With Bit Mask

IP.com Disclosure Number: IPCOM000057177D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Smith, CD [+details]

Abstract

A content addressable memory (CAM) cell is made of two distinct cascode current switched circuits (CCSCs). The first CCSC being a flip-flop (FF) or latch and the second CCSC being an Exclusive-OR with an 'override' input and an emitter follower output. This cell allows the CAM array to have adjustable row and column lengths with a minimum number of devices and cascode levels. The cell (Fig. 1) is described in the following. A00 (Fig. 2) is the data input for the latch. K00 is the clock or 'write/read not' (w/rn) input, and K01 is the compare argument input. L00 and L01 are the bit mask or override control inputs. Q10 is the latch's output. Q20 is the 'match not' output. Z02 and Z03 are voltage reference inputs. Y00 is a current source reference input. A00 has a voltage swing around the Z03 reference.