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Improved Cache Mapping Apparatus

IP.com Disclosure Number: IPCOM000057179D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Ngai, AY Ngai, CH [+details]

Abstract

A cache is usually a smaller but faster storage buffer and is implemented to avoid the long access time of main store. For this reason, a high cache hit ratio is desirable for a typical processor. A described algorithm, consisting of hashing addresses, minimizes paging between cache and main store and improves the cache hit ratio. (Image Omitted) A typical cache data flow consists of the following components: directory, cache, directory addressing, cache addressing and cache output circuitry. These components are connected as shown in Fig. 1. The cache is a subset of main store and is usually implemented as a high-speed buffer. The cache is made more flexible by mapping each real address into one of several cache locations. This technique is called congruency. The address mapping is performed in a table-called directory.