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Hardware Lock Bits Stored in Array Chip Disclosure Number: IPCOM000057199D
Original Publication Date: 1988-Mar-01
Included in the Prior Art Database: 2005-Feb-15

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Gilda, GD [+details]


Hardware lock bits are implemented in IBM 4381 dual processors with cache memories to prevent an instruction processing unit from accessing a cache page already in use, or updated by another instruction processing unit. This function is useful in a System/370 (S/370) environment for such functions as instruction retry and certain multiprocessing S/370 instructions. Implementation requires that all of the lock bits associated with a particular processor can be reset simultaneously. Therefore, implementation has previously involved storing the lock bits in a number of latches in logic chips because it was not feasible to reset all data stored in array chips simultaneously.