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Parallel Combining of Floating Point Incrementation in Multiple Computer Processing Disclosure Number: IPCOM000057271D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

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Heilper, A Norton, A [+details]


A technique is described whereby an integer fetch-and-add operation implements a floating point parallel incrementation, so as to eliminate serialization caused when multiple processors simultaneously attempt to increment a floating point variable. The concept is suitable for software, microcode or hardware implementation of a floating point incrementation instructions. In many parallel computer applications, such as those involving numeric equations, it is periodically necessary for all processors to increment a floating point value. In multiple processor applications, several processors can attempt to update the floating point value simultaneously. Therefore, it is architecturally necessary to ensure that the result of such updates obey "serialization principles".