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Algorithm to Implement Adders With Small Book Sizes Disclosure Number: IPCOM000057280D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

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Putrino, M Schwarz, EM Vassiliadis, S [+details]


One of the major concerns in logic design is the size of the books (logic gates) available in the technology that a function has to be implemented in. A study which describes an algorithm for an adder develops the implementing equations dependent on the limits of the technology used (in terms of book size), thereby developing an efficient implementation for any particular technology. The algorithm is based on the formulation of the SUM as follows.