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IMPROVED ZERO RESULT DETECTION WHEN USING a CARRY LOOK AHEAD ADDER

IP.com Disclosure Number: IPCOM000057304D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Goldberg, WD [+details]

Abstract

This article describes a technique which provides reduced gate count and increased speed of zero detection during subtract (compare) operations when using a carry look-ahead adder (CLA). When designing an adder that will be used for comparing two numbers a difficult problem is the method of zero result detection. The obvious solution to this problem is to use a large "OR" tree at the output of the "SUM" logic. However, this is expensive to implement and the delay is significant. An improved solution, when using a CLA, is the technique disclosed herein. The drawing is a block diagram of a CLA. The following definitions are made: "A" operand: A = a(0) a(1) ... a(n-1) "B" operand: B = b(0) b(1) ...