On-Chip LSSD System Clock Generation
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15
A clock generation circuit to be on an LSSD chip produces two output clocks from a single input. The two outputs are timed to minimize clock skew problems. As machine cycle times decrease, clock skew will play a more prominent role in determining the minimum machine cycle time. Disclosed is a technique that generates LSSD system clocks (C1 and C2) from a single clock source input primarily on array chips containing LSSD latches. A secondary consideration would be logic chips containing SRLs (Shift Register Latches). The major objective is to reduce the on-chip (local) clock skew between the C1 and C2 clocks. Chip-to-chip (global) clock skew is handled through separate methods.