Browse Prior Art Database

High-Speed Multi-Master Channel Interface

IP.com Disclosure Number: IPCOM000057315D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Chang, LL Colbourne, RJ Graybill, JH Hartsock, LM Ott, WB [+details]

Abstract

This article describes a high-speed multi-master channel interface (HSMCI) circuit between a bus master's local bus and a shared multi- master system bus. The HSMCI circuit is shown in block diagram in the drawing. It can be divided into two parts, system interface and local interface. The system interface portion is composed of an address register 2, system status signals 8, bus arbitration control 14 and 1 and a portion of data-in and data-out register/selector 3, 4, 5, and 6. The local interface side includes a portion of the HSMCI control 1 for local address decode and data interface, local direct memory access (DMA) request signal 13 and a portion of the data-in/data-out register/ selector. The uniqueness of this circuit is the buffered data register/ selector 3, 4, 5 and 6 arrangement.