Browse Prior Art Database

Dynamic RAM Controller

IP.com Disclosure Number: IPCOM000057335D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Bond, AL Hayes, EN Rydland, MA [+details]

Abstract

The article describes a controller for controlling a dynamic RAM. The controller and the dynamic RAM may be used with a microprocessor such as the INTEL* 80286. The controller performs several functions including RAM pump-up (or wake-up), RAM initialization, RAM read and write, and RAM refresh. Several enhancements that improve the performance versatility of memory capability are also provided. The figure shows a functional block diagram of the controller which is capable of addressing two megabytes of RAM. There are 21 input address lines and 9 output multiplexed (MUX) address lines. There are 4 RAS lines and 2 CAS lines to access up to four memory banks of 256K bytes each. Performance is enhanced because the refresh function is hidden or partially hidden from the microprocessor in one of two ways.