CMOS Differential Amplifier With Wide Hysteresis
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15
The article describes a circuit arrangement for a CMOS differential amplifier with wide hysteresis. The hysteresis is provided by a feedback N-channel field-effect transistor (FET) device connected in parallel with one of the differential pair FET devices. The CMOS differential amplifier includes a pair of differential N-channel FET devices T2 and T3. The source electrodes of devices T2 and T3 are biased to ground potential with a current source 2I. The gate electrode of device T2 accepts the positive input signal (VINP) while the gate electrode of device T3 accepts the negative input signal (VINN). The drain electrodes of devices T2 and T3 are connected by matched load transistors T4 and T5 to power supply Vdd. A third N-channel FET device T1 is connected in parallel with FET device T2.