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Low-Cost Clock Generation Circuit

IP.com Disclosure Number: IPCOM000057348D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Concha, F Leininger, JC [+details]

Abstract

A technique is described whereby a circuit generates three distinct clock signals while maintaining accurate pulse width and timings between the pulses along with a minimum of skew. The circuit is an improvement over previously used techniques in that when variable pulses are required loading restrictions placed on clock drivers and latches will not be affected. (Image Omitted) In prior art, clock generation circuitry caused the oscillator symmetry to vary greatly with the output load requirements. Large overshoots often occurred on all clock signals causing excessive ringing of the overshoot signals. The concept described herein provides a stable multi-clock generation circuit which not only eliminates prior art defects, but provides additional advantages. The clock generation circuit, as shown in Fig.