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Improved "Stuck-Fault" Testing of Microprocessor-Based Circuitry

IP.com Disclosure Number: IPCOM000057354D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Becker, D Boudreaux, RP Crouse, RS Kreitzer, S [+details]

Abstract

A technique is described whereby "Stuck-Fault" testing of microprocessor-based logic circuitry is enhanced through the use of interactive fault diagnostics, thereby eliminating the need for software models which were previously required to create testing patterns. Typical logic circuit "Stuck-Fault" testers are intended to operate on logic circuits by driving predefined data pattern sequences into physically accessible probe points. Testing is performed by repeatedly measuring the outputs for accuracy comparisons against a dataset of predicted outputs. The datasets defining the input sequence of the patterns and the resulting outputs are usually created by running test-pattern generation software tools against a software representation of the circuit under test.