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Polish Stop Structure for Oxide-Filled Semiconductor Trenches

IP.com Disclosure Number: IPCOM000057366D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Koburger, CW [+details]

Abstract

A process is disclosed for using a refractory metal and/or refractory silicide as a planarization polish stop for polishing oxide materials used to fill shallow isolation trenches fabricated in the CMOS technology. Silicon dioxide is the obvious choice of insulators to use for filling shallow isolation trenches. Unfortunately, polishing processes do not work well for structures wherein the polish step is intended to remove oxide, due to a poor polish rate ratio between oxide and nitride (etch stop). This leads to cross-wafer uniformity problems, difficulties in removing oxide over large untrenched regions, and end point detection problems.