Browse Prior Art Database

Multilevel Metallized Semiconductor Chip Edge Seal

IP.com Disclosure Number: IPCOM000057370D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Chesebro, DG Totta, PA [+details]

Abstract

A terraced metal structure "barrier reef" or a narrow band of metal "wall" around the perimeter of a semiconductor chip permits metal levels to be designed up to the chip's active edge without risk of polyimide or photoresist thinning or mechanical damage caused by dicing, both of which can lead to a corrosion risk caused by metal exposure. When polyimide insulation is utilized in multilevel metal processes, removal of the polyimide from the kerf area is very difficult. Total removal is necessary before dicing to prevent mechanical damage (polyimide delamination) which leads to corrosion of fine metal lines near the chip's active edge. The use of planar polyimide films and stud interlevel connections rule out the ability to clear out the kerf polyimide during normal patterning operations used to define internal chip structures.