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Logic Design for Improving Data Transfer Performance of Single-Transfer Mode Direct Memory Access Devices Via Use of Pseudo Microprocessor Memory Cycles Disclosure Number: IPCOM000057375D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

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Boudreaux, RP Crouse, RS Pita, F [+details]


This article describes a technique for speeding up direct memory access (DMA) transfer operations in a processor having logic intercept bus arbitration signals exchanged between the system microprocessor and the DMA controls and generate fast pseudo memory cycles when the DMA relinquishes the bus. This causes the DMA to quickly re-arbitrate and perform another transfer. In some microprocessor based logic design applications with DMA capability, it is critical that the DMA very large scale integration (VLSI) device not be allowed to enter a burst mode when transferring data. Burst means that the DMA device acquires the memory data bus from the microprocessor and then keeps it for as many consecutive memory cycles as is necessary to transfer a string of data bytes that it has been requested to transfer.