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Two-Dimensional Fan-Out Using Transverse Via Technology Disclosure Number: IPCOM000057376D
Original Publication Date: 1988-Apr-01
Included in the Prior Art Database: 2005-Feb-15

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Dougherty, WE Greer, SE [+details]


This is a technique for expanding connections from a semiconductor chip by stacking multiple ceramic layers formed in accordance with transverse via technology. In the manufacture of a substrate for the mounting of semiconductor chips, one technique is to utilize a plurality of sheets of ceramic having conductor patterns screened thereon and assembled in a face-to-face relationship with the patterns running from a central portion of the substrate to form a mounting location for the chips, and "fanning-out" or redistribution to form locations on the same or opposite side of the mounting location for connection to I/O pins. This transverse via technology technique is described in U.S. Patents 4,193,082 and 4,202,007.