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Advanced Bit Mask Control Circuit

IP.com Disclosure Number: IPCOM000057421D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Aoki, Y Takayanagi, K [+details]

Abstract

This article describes a bit mask control circuit which uses two bit mask registers to improve performance of write operations of graphics data into an all-points-addressable (APA) memory. This circuit is particularly useful for continuous data movement in which two mask data are required for start and end edges, respectively. In the drawing, an MPU data bus, which may be a 16-bit bus, is connected to a rotator 10, a first bit mask register 12 and a second bit mask register 14. The rotator 10 receives and rotates data to be written into an APA memory. The bit mask registers 12 and 14 receive respective mask data or patterns for use at the start and end edges of graphics data. An address calculation unit 16 selects either one of the registers 12 and 14 through a multiplexer 18.