CMOS Read-Only Memory Column Line Repeater
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15
A CMOS read-only memory (ROM) circuit is shown which reduces support circuitry and wiring complexity by eliminating the need for second level metal wiring or additional repetitive bit decoders. Second level metal or repetitive bit decoding schemes are utilized in some CMOS ROM designs to limit the RC delay of a column line. During standby, the ROM word lines are grounded while the bit and column lines are restored to Vdd. To select a cell, a column line is held at ground and a word line along the column line at ground is pulled to Vdd. Adjacent bit lines are then discharged through the word line transfer device to the grounded column line. Signal development is limited by the RC delay down the column line, particularly when the column line is underpassed.