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Testing Parity Check Circuits

IP.com Disclosure Number: IPCOM000057425D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Bock, DW Doettling, G Kumpf, W Rudolph, P Schulze-Schoelling, H [+details]

Abstract

For testing the function of parity check circuits, the transferred parity bit P or the parity bit Pg, generated from the transferred data bits, is artificially falsified. For testing, the check circuit for a data flow path with 8 data bits D0 to D7 and a parity bit P is extended by a XOR gate 4 (Fig. 1). Each check circuit, associated with a register, say, register A, is tested by an instruction which artificially falsifies the parity of the transferred parity bit P in XOR gate 4. As a processor generally comprises a large number of parity check circuits - one for each byte - and there are several bytes for each register and many registers, a large number of instructions is required for testing the check circuits. This reduces the number of instructions normally available for the functional code.