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RAM With Variable Data Width for Write and Read Operations

IP.com Disclosure Number: IPCOM000057428D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Clemen, R Loehlein, WD Tong, M [+details]

Abstract

In a conventional random-access memory (RAM) the data to be written and read are transferred through the same bit switches which are located between the data input/ output buffers and the memory cell array. The bit switches are generally realized by a CMOS transmission gate. However, such a structure is not suited for fast byte-organized RAMs, particularly if the data width is different during the write and read operations. With a 72-bit data bus, for example, a common write/read switch would necessitate that the data input buffers be located next to the output buffers, both attached to the same internal 72-bit data bus. As a result, the 72-input data lines would have to cross this internal bus or the sense lines, which would further increase the bus load and delay.