CMOS Gate With Low Inductance of the Power Supply Lines
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15
This article describes a novel CMOS (complementary metal-oxide semiconductor) gate array structure for reducing noise voltages caused by high current peaks. Conventionally designed gate arrays are schematically illustrated in Fig. 1. Straight transistor gates are positioned above the respective P+ and N+ doped regions transversely to the N- and P- conductive stripes embedded in the substrates. Power supply lines VH and GND are arranged transversely to the gates. As a result of the way in which the transistors are arranged, lines VH and GND are spaced very widely (50 mm) from each other.