Browse Prior Art Database

Write Read Access for RAM Update

IP.com Disclosure Number: IPCOM000057432D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Hawes, AJ Taylor, JL [+details]

Abstract

In a dynamic random-access memory (RAM) for an all-points-addressable (APA) graphics display, timing difficulties occur on read-modify-write (RMW) cycles. Here, it is recognized that many APA store accesses involve sequential addressing of alternating reads and writes in the same page access and construct a series of RMW cycles for a series of WR cycles using write, change address, read to provide relaxed timing requirements. Most dynamic RAM specs include the following types of cycles: 1. Page read cycle. 2. Page write cycle. 3. Read-modify-write cycle. The read-modify-write cycle is really a read cycle and a late- write cycle crushed together. This crushing together causes timing problems on the data bus associated with turning the data bus to the RAM on after the read but in time for the write.