Method for Obtaining Low Resistance and Low Capacitance Metalization Using Single Metal Deposition
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15
Customized metalization for VLSI circuits and memory arrays is reported which provides the circuit designer with the ability to define low resistance and low capacitance lines on a line-by-line basis in the same wiring plane. As VLSI circuit dimensions and layer thicknesses are reduced, low capacitance and low resistance line requirements are compromised since low capacitance requires very thin metal layers while low resistance requires thicker metal layers. When a metal wiring level is deposited, it should be thick enough to obtain the minimum resistance required for the minimum dimension line. A first mask step is used to define the low resistance lines, as shown in Fig. 1. The metal is etched to an appropriate thickness in areas not protected by the first mask.