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Optimum Metal Line Structures for Memory Array and Support Circuits Disclosure Number: IPCOM000057460D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

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Related People

Cronin, JE Holland, SP Kaanta, CW [+details]


A process sequence is described which will provide for low resistance interconnect lines in the logic support areas of a semiconductor chip and simultaneously provide for low capacitance interconnect wiring in the memory array portion of the same chip. VLSI memory array wiring requires low capacitance bit and word lines, while the memory support circuits require low resistance interconnect wiring at the same metal level. An ideal wiring scheme for such memory chips would reduce bit and word line capacitance by reducing line height and width in the memory areas and would reduce interconnect line resistance by increasing line height and width in the logic support areas. A solution to this problem is a composite line structure at the first metal level (M1).