Browse Prior Art Database

Simplified Lightly Doped Drain Process

IP.com Disclosure Number: IPCOM000057464D
Original Publication Date: 1988-May-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Koburger, CW Lasky, JB Roberts, S [+details]

Abstract

A novel process is shown for forming a lightly doped drain (LDD) NFET in a CMOS process. The process uses fewer masking steps than the conventional process. In addition, the total required spacer width is minimized. Figs. 1A-1D show a conventional process. Only that portion of the process relating to fabrication of the NMOS device is discussed. After definition of the gate electrode, a thin sidewall spacer (first spacer) is formed. A mask (BP mask) is applied which blocks the p-channel devices, and the lightly doped region of the NMOS junction is formed (shallow implant), as shown in Fig. 1A. The BP mask is removed, as shown in Fig. 1B, and a second spacer is formed. Next a heavily doped portion of the N+ junction is formed (deep implant), as shown in Fig. 1C.